Since the development of the first integrated circuit device, the technology of semiconductor fabrication has focused on minimizing the feature size of semiconductor devices. With the advancements made in processing technologies such as deposition, lithography, etching, and thermal treatment, the packing density of integrated circuit chips has greatly increased. A single chip manufactured using the present semiconductor fabrication technology may include millions or even billions of devices such as transistors and capacitors. To accomplish this, the feature size of integrated circuit devices has been scaled down to a submicron level.
When semiconductor devices are densely arranged on an integrated circuit chip, the conductive interconnections between such devices must be scaled down accordingly. All of the conductive pathways (typically, polysilicon or metal connections) between devices must be scaled down in width, without degrading the operating characteristics of the integrated circuit. When used to connect submicron size devices, the interconnections must provide defect-free contact between conducting and connecting members.
The interconnections on integrated circuit chips are generally constructed to have several layers of metal pathways. With the increased packing density of modern semiconductor chips, three or more layers of metal connections are commonly used for constructing the entire circuit. The connections between metal layers and underlying conductive regions of polysilicon are provided by means of conductive plugs. FIG. 1 shows a semiconductor structure 100 which includes a semiconductor substrate 110 having a conductive region 112 to be electrically connected with other conductive regions in structure 100. A dielectric layer 114 is formed over the substrate 110 and subsequently pattern etched to define a contact hole 115 therein. After the deposition of a conductive wetting layer 116 and a conductive diffusion barrier layer 118, a filling layer 120 of a conductive material is deposited into the contact hole 115 for the purpose of forming a contact plug 122, which provides an electrical connection to conductive region 112.
As shown in FIG. 2, the filling layer 120 is then etched back so that the contact plug remains in the contact hole 115 for the purpose of making a conductive connection with an overlying metal layer deposited in a subsequent processing step. Ideally, the filling layer 120 is etched back until the portion of conductive material outside the contact hole 115 is removed and the portion inside the contact hole 115 remains (i.e., the top surface of the portion of the filling layer remaining within the contact hole is even with the top surface of the dielectric layer 114).
A conventional method of filling a contact hole is to deposit a layer of metal over dielectric layer 114 and then to etchback the metal layer to create a "plug" in the hole. For example, and not by way of limitation, the metal may be tungsten, aluminum, aluminum-copper, aluminum-silicon-copper, or aluminum-silicon. Regardless of the conductive material used, it is difficult to control the etchback process so that the conductive residue is completely removed from the upper surface of the dielectric layer, while leaving the contact hole completely filled with conductive material. If the etchback process is performed until the conductive residues 210 (shown in FIG. 2) are completely removed, plug loss is found to result in a shortened contact plug 224. By contrast, an etchback process without plug loss may result in a significant amount of residue remaining outside the contact hole. The remaining residues 210 may create undesired current leakage or short-circuiting problems in the final product.
In their paper entitled "Tungsten Etch Technology for Submicron Devices" (Advanced Metallization for ULSI Applications Proceedings of Conference, pp. 463-469, 1992), Ivo Miller et al. disclosed the above problem in a tungsten etchback process. Miller et al. describe that, in a blanket deposition/etchback scheme, the primary objective is to leave a via or contact completely filled with tungsten. However, the problem of microloading (a change in the local etch rate relative to the location of the material being etched on the substrate) is of paramount importance, and the paper presents detailed descriptions of a method for reducing the microloading effect. Extensive work was performed in an attempt to minimize the effect of microloading by introducing polymerizing chemistries at endpoint and by reducing etchant concentration. However, Miller et al. point out that these approaches also have an impact on system cleanliness and on wafer throughput. Miller et al. developed and characterized a fluorine-based tungsten etchback process for a single wafer plasma etch system. The effects of temperature on the microloading effect and on the etch selectivity toward tungsten relative to titanium nitride were evaluated and summarized. Although the mechanism was not discussed in detail, Miller et al. found that control of the processing temperature assists in controlling tungsten plug loss and tungsten: titanium nitride etch selectivity. Miller et al. proposed a method for controlling the microloading effect and the tungsten to titanium nitride etch selectivity using a reduced processing temperature, allowing optimum process latitude without excessive tungsten plug or titanium nitride barrier layer loss.
U.S. Pat. No. 5,641,710, issued Jun. 24, 1997, to Wang et al., discloses a tungsten etchback process with an accompanying annealing process. A post-reactive ion etch (RIE) anneal is performed in a nitrogen ambient to remove moisture from the surrounding dielectric layers of plugs and also to form a protective, nitrogen-containing tungsten layer to fill the crevice in the tungsten plug. However, Wang et al. does not address the plug loss problem in tungsten etchback processes.